module Counter_Design_TB;
	reg clock,clear;
	wire [3:0] out;
	initial
	$monitor($time,"count=%b,clear=%b",out[3:0],clear);
	
	Counter_Design MVP(out,clock,clear);
	
	always
	begin
		clear=1'b1;
		#15 clear=1'b0;
		#200 clear=1'b1;
		#50 clear=1'b1;
	end
	
	initial
	begin
		clock=1'b0;
		forever #5 clock=~clock;
	end
	
	initial
	begin
		#400 $Finish;
	end
	
endmodule
